EDN

Lower power, high-performance architecture for AMBA 3 AXI On-Chip Interconnect is unveiled

Winchester, UK – Synopsys, Inc., (Mountain View, California) software and IP specialists for semiconductor design and manufacturing, has enhanced its DesignWare IP for the ARM AMBA 3 AXI interconnect ...
EDN

Self-timed interconnect solution supports AXI bus protocol

SAN FRANCISCO — EDA and intellectual property (IP) startup Silistix Ltd. has added support for the on-chip AMBA AXI bus protocol to the company's synthesized self-timed interconnect technology, ...
Design-Reuse

Silistix Self-Timed Interconnect Solution Adds Support for AXI Bus Protocol

Extends Designer Use of Popular AMBA Buses for Asynchronous Interconnect on SoCs SAN JOSE, CA -- July 17, 2006 -- Silistix, a provider of innovative software for on-chip communications solutions, ...
Business Wire

PLDA Announces Two Innovative vDMA Engine IP Solutions, Delivering Robust Performance and Scalability across a PCIe Link or AMBA AXI Fabric

SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in PCI Express® IP solutions, today announced two innovative DMA engine solutions designed to manage large and heterogeneous data traffic ...
Semiconductor Engineering

Reduce Power, Area And Routing Congestion

This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare Interconnect Fabric for the ARM® AMBA 3 AXI while minimizing ...
Electronic Design

EDA News

To accelerate adoption of amba axi technology, ARM and Synopsys are collaborating on applicable verification IP. AMBA AXI technology is a next-generation on-chip ...
Electronic Design

On-Chip Interconnect Scheme Reaches For Broader Appeal

Having found some success with high-end SoC makers, such as Texas Instruments and its OMAP cell-phone processors and Samsung with its HDTV chips, Sonics is looking for new homes for its Smart ...
Semiconductor Engineering

The Interconnect Game

Having a single bus protocol is something most SoC engineers can only dream about. Reality is often a jumble of protocols determined by the IP they use, which can slow down a design’s progress. The ...
Design-Reuse

Synopsys Introduces Lower Power, High-Performance Architecture for AMBA 3 AXI On-Chip Interconnect

New DesignWare IP Hybrid Architecture Reduces Area, Power Consumption and Routing Congestion for High-Performance AMBA Interconnect-Based Designs MOUNTAIN VIEW, Calif. -- April 15, 2009 -- Synopsys, ...