Open-source tools and multi-project wafer (MPW) shuttles democratize chip design for low cost. Small circuits, both analog and digital, are accommodated by embedding them as “tiles” or “clusters” into ...

For most system-on-chip (SoC) designs, the most critical task is not RTL coding or even creating the chip architecture. Today, SoCs are designed primarily by assembling various silicon intellectual ...

For decades, the design of leading-edge chips has been a high-wire act—balancing tight deadlines, sophisticated workflows, and the relentless need to consult scattered, often outdated, sources of ...

Why it matters: As powerful as AI may be, many industries are still struggling to find clear-cut applications that make a measurable, demonstrable difference. Thankfully, that is not the case when it ...

Experts at the Table: Semiconductor Engineering sat down to discuss the advantages and challenges in using AI in designing chips, with Chuck Alpert, Cadence Fellow; Sathish Balasubramanian, head of ...

More companies are seeking to employ System-on-Chip (SoC) designs for future Generative AI products. To help meet these needs, network-on-chip IP company Arteris has expanded its tiling capabilities ...

Since their early introduction a few years ago, AI-powered features have become a mainstay of EDA (Electronic Design Automation) tools. Many of the complex yet potentially tedious tasks silicon ...

A new technical paper titled “A Vertically Integrated Framework for Templatized Chip Design” was published by researchers at University of Southern California. “Developers who primarily engage with ...