Semiconductor Engineering

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)

A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...
Forbes

Spin Memory Selector Improves DRAM, ReRAM And MRAM Density, New Microchip SSD Controller

Spin Memory, a magnetic random-access memory (MRAM) startup announced a new semiconductor technology that could allow a dramatic improvement in DRAM as well as emerging memory technologies, such as ...

Marvell Technology And Astera Labs: Quiet Winners From Surging Memory Prices

Astera Labs and Marvell are poised to gain from surging memory prices via memory controllers. See more on ALAB and MRVL stock ...
The Next Platform

Accelerating Compute By Cramming It Into DRAM Memory

Perhaps the biggest task that processor and system designers have to wrestle with these days is how to keep heavily cored and massively threaded processors fed with data. Modern CPUs have anywhere ...
Electronic Design

A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!

The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...

The Daring Attempt to End the Memory Shortage Crisis

The supply shortage of the RAM needed to build phones and PCs isn’t going away. But a few companies have a plan to solve it.
Semiconductor Engineering

Memory Buffer Chips: Satisfying Amdahl’s Law To Sustain Moore’s Law

Moore’s Law, the observation that the available transistors in an integrated circuit doubles every two years, has driven the semiconductor and IT industries to unparalleled growth over the last 50+ ...