EDN

FPGA Interfaced with HD44780

The project employs Finite State Machine (FSM) to interface a typical HD44780 Text LCD to an FPGA using delay elements. The project employs Finite State Machine (FSM) to interface a typical HD44780 ...
Business Wire

Aldec Provides Finite State Machine Coverage for Verification of Safety-Critical FPGAs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc. announced today the latest release of its mixed-language, FPGA Design & Simulation platform, Active-HDL™ 10.4, providing Finite State Machine (FSM) ...
Design-Reuse

Aldec Releases Automated Static Linting and CDC Analysis for Microchip FPGA and SoC FPGA Designs

Henderson, NV – February 6, 2023 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated its popular linting tool ALINT-PRO ...
Business Wire

InterMotion Technology Boosts IP Verification Productivity for Lattice Semiconductor’s CrossLink FPGA Family Using Aldec’s Active-HDL

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology has ...
Electronics Weekly

How reliable is your FPGA-based system?

As FPGA die geometries shrink, larger amounts of the die can be hit by a single radiation particle, making the design more susceptible to the impact of radiation-induced errors that cause bit values ...
Design-Reuse

InterMotion Technology boosts IP verification productivity for Lattice Semiconductor's CrossLink FPGA family using Aldec's Active-HDL

Henderson NV, USA – March 24, 2020 – Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, today announced that InterMotion Technology ...