Business Wire

Aldec Provides Finite State Machine Coverage for Verification of Safety-Critical FPGAs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc. announced today the latest release of its mixed-language, FPGA Design & Simulation platform, Active-HDL™ 10.4, providing Finite State Machine (FSM) ...
Design-Reuse

Latest Synplify FPGA Synthesis Software Offers New High-Reliability Features and Improves Productivity for FPGA-Based Prototyping

MOUNTAIN VIEW, Calif., April 2, 2012 -- Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today ...
Design-Reuse

Synplicity Launches ReadyIP Program: The Industry's First Universal, Secure IP Flow for FPGA Implementation

SAN JOSE, Calif.--April 15, 2008 --Synplicity®, Inc., a leading supplier of innovative IC design and verification solutions, today announced the ReadyIP Initiative, a program that takes aim at ...