Driven by the need to objectively measure the progress of their verification efforts and the contributions of different verification techniques, IC designers have adopted coverage as a metric. However ...

Over the last ten years, we have seen tremendous progress in technologies for formal verification of the behavior of RTL designs. Today, these formal technologies are vastly more thorough than ...

How formal verification is able to find bugs before signoff. Formal verification’s ability to mathematically prove exhaustively that a chip design meets a set of assertions. Formal techniques are ...

The first time I came into contact with the concepts of a digital hardware description language (HDL) and digital logic simulation, I inherently understood how it all “worked.” The idea that the ...

Over the last twenty years, formal verification has grown from a niche technology practiced only by specialists to an essential part of mainstream chip development. Along the way, several advances ...

Formal verification associated with assertions is a well known approach to functional verification of SoC digital circuits. This technique bears several advantages over dynamic-based solutions, but ...

Standardization work is underway to develop assertion languages (for example, PSL and SystemVerilog Assertions) to address the shortcomings of natural language specification. The goal in creating ...

Formal methods provide a rigorous mathematical foundation for the specification, development and verification of medical device software. This approach enhances both reliability and safety, which are ...

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.