New Electronics

IP test silicon for PCI Express 6.0 specification on TSMC's N5 process

Cadence Design Systems is making IP immediately available that supports the PCI Express (PCIe) 6.0 specification on the TSMC N5 process. The IP consists of a high-performance DSP-based PHY and a ...
Business Wire

Cadence Accelerates Cloud Hyperscale Infrastructure with Third-Generation 112G-LR SerDes IP on TSMC’s N5 Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process for hyperscale ASICs, ...
Design-Reuse

Synopsys DesignWare IP Achieves Broad Industry Adoption with Multiple First-Pass Customer Silicon Successes on TSMC's N5 Process

High-Quality Interface and Foundation IP Adopted by More Than 20 Leading Semiconductor Companies, Across Range of Automotive, Mobile and High-Performance Computing Markets MOUNTAIN VIEW, Calif., June ...