EDN

Physical RTL optimization solves problems early

While most of the ASIC industry is focused on solving timing and congestion problems at the netlist level, LSI Logic has developed and deployed an innovative methodology to resolve these physical ...
EDN

RTL coding architecture affects power estimation & analysis

A well thought out design flow for SoCs ensures that the resulting device meets the requirement of low power dissipation. To meet these goals at the device level, individual modules (or components of ...
Semiconductor Engineering

Top Five Trends In RTL Signoff

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage ...
Design-Reuse

Adaptive Silicon and Atrenta Partner to Provide RTL Coding Rules for Programmable Logic Cores

LOS GATOS, Calif./SAN JOSE, Calif. - October 8, 2001 - Adaptive Silicon, Inc. (ASi) of Los Gatos, Calif., and Atrenta Inc. of San Jose, Calif., today announced that ASi is developing an Adaptive ...
Semiconductor Engineering

Achieving RTL-To-Netlist Equivalence

Running quality tests and regression at RTL level, and even fixing all discovered design bugs does not guarantee the flawless hardware design. To make sure there are no bugs in the target hardware, ...
Electronic Design

Predictive-Analysis Tool Sniffs Out Gate-Level Problems In RTL Code

Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only ...
Electronic Design

Tool Generates RTL Code From Untimed C++

The complexity of compute-intensive applications is driving the move to system design at the algorithmic level. With the release of the Catapult C synthesis tool ...
Design-Reuse

Real-World Reuse: RTL Recycling

In the real world of electronic product design, time-to-market can have a large impact on success. To facilitate production speed, RTL from existing projects is often recycled for use in the new ...
Electronics Weekly

In FPGA design timing is everything, says Synopsys

When your FPGA design fails to meet timing performance objectives, the cause may not be obvious. The solution lies not only in the FPGA implementation tools’ talent in optimising the design to meet ...
New Electronics

Addressing safety critical FPGA designs

Field-programmable gate arrays (FPGAs) are the dominant hardware platform in many safety-critical, low-volume applications, including aerospace and nuclear power plants (NPPs). Modern FPGA devices ...