Modern semiconductor fabrication involves aligning silicon wafers and photolithography masks to nanometre precision. As the industry shifts from using 200 mm diameter wafers to 300 mm wafers, ...

Improving on product overlay is one of the key challenges when shrinking technology nodes in semiconductor manufacturing. . . . With smart placement of alignment mark pairs in the X and Y direction, ...

An optical method for mask alignment in double-sided lithography has been developed by a team at the University of Hagen in Germany (Appl. Opt. 40 5052). The technique, which is based on the ...

One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., ...

Wafer-to-wafer bonding is an essential process step to enable 3D devices such as stacked DRAM, memory-on-logic and future CMOS image sensors. At the same time, minimizing the dimensions of TSVs, which ...