GitHub

7 Segments using Logic Gates

VHDL code that drives a seven segment display using logic gates input ports B3, B2, B1, B0, and an output port Dot along with seven segment display output ports A, B ...
TechRepublic

Design of Cache Memory with Cache Controller Using VHDL

The authors report on the design of efficient cache controller suitable for use in FPGA-based processors. Semiconductor memory which can operate at speeds comparable with the operation of the ...
IEEE

Distributed Algorithms for Boolean Equations Over Networks

Abstract: In this article, we study systems of Boolean equations over a network, where each node in the network possesses only one Boolean equation from the system. The Boolean equation assigned at ...
IEEE

Reconstructing the State of a Boolean Control Network via State Feedback

Abstract: The goal of this article is to investigate under what conditions a Boolean control network admits a state feedback control law that makes the resulting Boolean network reconstructible.
GitHub

Realtime Audio Processing on Artix-7 FPGA

This project was created to demonstrate the capabilities of the Artix-7 FPGA at course Digital Design at University of Ljubljana FRI. The project uses the Digilent Nexys 4 DDR board, which has a ...